After a code is running on FPGA (i.e. after bitstream generation) how to store the output of a particular port in Vivado.
Hello again,
So I am using an FPGA and Vivado Software. After bitsream genration my code is running perfectly on the FPGA.
My doubt is that can I store any output port or signal as any kind of file in Vivado directly ?
Not at simulation level but at implementation level ?